Design Engineer

Job Description

What we’re looking for:

Person will be responsible for DFT Architecture including JTAG functionality, boundary scan, hierarchical scan, at- speed testing, I/ O testing requirements, MBIST and Repair, implement test logic for analog macros. Person should also be responsible to develop firmware driven cost-effective test strategies methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on ATE. Person should be capable of generate and debug DFT patterns on tester.

Skills you’ll need:

• Expert knowledge of DFT architecture on complex Design with multiple clock domains.
• Experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, Bridging fault and Small delay defects .
• Experience in industry standard DFT tools - Mentor Tessent suite, Synopsys DFT compiler.
• Expert knowledge on scan coverage improvement and Test time reduction.
• Experience with standard JTAG protocol and Boundary scan.
• Should have participated in successful tapeouts of DSM SoC/ASIC chips at 40nm or below and achieved test targets.
• Experience working with cross functional global teams
• Experience in Low-Power DFT requirements.
• Experience in Low-Power MBIST architectures and Memory testing.

Required Education/Experience:

3-5 years in Industry

Bachelors/MS in Electrical Engineering, or equivalent

• Experience of working with Advantest, Teradyne testers.
• Experience in DFT related RTL integration.
• Excellent debugging and Scripting skills.
• Excellent communication and analytical skills
• Mentoring skills
• Exceptional problem-solving skills

Benefits & Perks :

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Employee Stock Purchase Plan (ESPP)
• Insurance plans with Outpatient cover
• Flexible work policy